; driver for MDP5011 ; (c) copyright GP Eckersley ; released under terms of ; GNU General Public License Version 3 as published by ; the Free Software Foundation ; Id: pic18pwm.a18,v 1.13 2010/12/28 21:13:57 daddio Exp $ ; works, no voltage control 000, ; bugs pictalk 001 ; Id: pic18pwm.a18,v 1.16 2010/12/29 22:35:50 daddio Exp $ ; fixed stack set ; Id: pic18pwm.a18,v 1.18 2010/12/30 03:16:05 daddio Exp $ ; set scaling for 16 v dc supply ; Id: pic18pwm.a18,v 1.23 2011/01/01 11:39:57 daddio Exp $ ; Tested with 16 volt supply runs reqttm=0x330 @ 20 Torr ; to run turn on eninc and enfb in aflags ; Id: pic18pwm.a18,v 1.26 2011/01/03 23:22:11 daddio Exp $ ; starts with no overcuurent or glitches if sequenced aflags 0.4,0e ; Id: pic18pwm.a18,v 1.29 2011/01/10 09:08:11 daddio Exp $ ; macros for add/acc/shift ; Id: pic18pwm.a18,v 1.33 2011/01/10 11:38:32 daddio Exp $ ; reasonably accurate version ; Id: pic18pwm.a18,v 1.36 2011/01/14 11:19:01 daddio Exp $ ; slews to 116 without much overshoot ; $Id: pic18pwm.a18,v 1.37 2011/01/14 13:09:34 daddio Exp $ ; Improvements needed ; Back-EMF is too course ; PWM to fractional values ; Startup sequence ; Led speed indicator ; Analog inputs ; list e=2 ; list p=16c84 ;list p=16c84 include ; internal ram allocations ; Following are general purpose storage mpad = 020 rsm macro lbl,cnt lbl equ mpad mpad = mpad+cnt endm udata tmp0 res 1 tmp1 res 1 tmp2 res 1 tmp3 res 1 tmp4 res 1 tmp5 res 1 tmp6 res 1 tmp7 res 1 savew res 1 savest res 1 savefsr res 2 sampleptr res 1 clock_time equ 80 ; 8 microsec; / 64 ;14 is about minimum, 40(064) is 64 * 16 = 4 microsec/cycle ; This is the main interrupt cycle time T_int ; power_flags res 1 vvtmp0 res 1 ; Stores data to be sent vvtmp1 res 1 ; Following are general purpose storage vvtmp2 res 1 vvtmp3 res 1 vvtmp4 res 1 vvtmp5 res 1 vvtmp6 res 1 pntb equ 3 ; no of bits for current table address pntc equ 1<=0 movff prma+lctr,prmb+lctr lctr = lctr-1 endw endm shrn macro prma,num ; signed shift of num bits to the right lctr = num-1 rlcf prma+lctr,w ; sign bit to carry while lctr>=0 rrcf prma+lctr,f lctr = lctr-1 endw endm shln macro prma,num ; shift of num bits to the left lctr = 0 clc while lctr < num rlcf prma+lctr,f lctr = lctr+1 endw endm mulh1 macro totres,prma,prmact,prmb,lprmb,result,addsub,addsubc prmbct = 0 while prmbct=0 clrf vvtmp4 movfw indrvvv+3 addwf errttm+2,w movwf drvvv cpfsgt vvtmp4 ; test lower limit < w bra tstupl subwf vvtmp4,w addwf indrvvv+3,f bra adjdun tstupl cpfslt vvtmp3 bra adjdun cpfseq vvtmp3 bra ddd bra adjdun ddd subwf vvtmp3,w addwf indrvvv+3,f adjdun movwf vvtmp5 fbdone noinc3 movfw clock_0+1 subwf tick1,w jnz scandun ; every 2048 muSec incf tick1,f jnz scandun incf tick1+1,f ; comes here on average every 4096/3276.8 microseconds with 16/20 mHx xtal, missing slots are queued incf cycnt,f ; incf portd,f ; ; pid loop movfw cycnt andlw 3 jnz scandun scandun return udata_shr 0a00 _stack res 0eff-0a00 _stack_end end